1. Field of the Invention
The present invention relates to a semiconductor memory having transistor cells each of which stores multiple bits, and a method of manufacturing such semiconductor memory.
2. Description of Background Art
Recently, nonvolatile semiconductor memories such as flash memories are widely applied to electronic appliances such as a mobile telephone. In order to promote size reduction and larger information capacity of the electronic appliances, it is required to miniaturize the semiconductor memory and increase the storage capacity of the semiconductor memory. Thus, there should preferably be implements the multiple-bit configuration of a cell transistor that allows two or more bits of information to be stored in a single cell transistor. The nonvolatile semiconductor memory described in US 2004/0169219 A1, filed by the assignee of the present application, has cell transistors each of which comprises a pair of floating gates that are electrically isolated and stores two bits (four values) of information.
FIG. 42 shows a cell transistor with a multiple-bit configuration taught in US 2004/0169219 A1. The cell transistor 100 comprises a control gate CG (Word Line), a pair of diffusion regions 101 that serves as the source region and the drain region, a projection 103 formed on a silicon substrate 102. When the control gate CG, the source and the drain regions are supplied with predetermined voltages, a channel is generated in the surfaces of the top and sides of the projection 103. In the operation to write information in the cell transistor 100, some electrons (charged particles) in the channel are supplied with enough energy to become hot electrons that can pass the pass the potential barrier in a first insulation layer 104 and flow into a drain side floating gate. In the operation to read the information from the cell transistor 100, the electric current flowing in the channel (drain current) is modulated in accordance with the amount of the electrons in the source side floating gate. In deleting the information in the cell transistor 100, there is no channel in the projection 103, so the electrons in the floating gates FG1, FG2 are discharged to the control gate CG through a second insulation layer 105 by FN (Fowler Nordheim) tunneling.
In manufacturing the cell transistor 100, the surface of the cell transistor 100 in the area on which the control gate CG is formed becomes flat. That is, the top surface of the second insulation layer 105 on the floating gates FG1, FG2, and a top surface of a third insulation layer 106 on the projection 103 become flat. In the third insulation layer 106 formed between the projection 103 and the control gate CG, a silicon oxide layer (SiO2) 106a, a silicon nitride layer (Si3N4) 106b and the silicon oxide layer (SiO2) 106c are layered in this order, so the third insulation layer 106 is relatively thick. When the third insulation layer 106 becomes thick, a large voltage needs to be applied to the control gate CG in order to control generation of the channel in the projection 103. Moreover, the following problems will occur as well.
The silicon nitride layer 106b serves as the mask in implanting impurity ions in the diffusion regions 101, and as the stopper in CMP (Chemical Mechanical Polishing) process to flatten the top surface of the region including surface oxides and the floating gates FG1, FG2. Since the silicon nitride layer 106b needs to be thick to work as the mask and the stopper, the silicon nitride layer 106b remains in the insulation layer 106 after the above processes. The dielectric constant of the silicon nitride layer 106b is much higher than that of the silicon oxide layers 106a, 106c, and the large area of the silicon nitride layer 106b faces the floating gates FG1, FG2 due to its large thickness. As a result, the silicon nitride layer 106b exists near the channel in the projection 103 via the silicon oxide layer 106a, and a part of the hot electrons enters the silicon nitride layer 106b and are captured (trapped) therein writing the information. Once the electrons are trapped, the electrons are localized in the silicon nitride layer 106b, so it is difficult to remove such electrons in the data erasing mode. Accordingly, by repeating to write and delete the information, a lot of electrons are trapped in the silicon nitride layer 106b, and thus the threshold voltage of the cell transistor 100 increases.
Even if the possibility to trap the electrons in the silicon nitride layer 106b is not considered, the silicon nitride layer 106b affects the operation of the cell transistor 100. As mentioned above, a large area of the silicon nitride layer 106b faces the floating gates FG1, FG2, and the silicon nitride layer 106b has high dielectric constant. Thus, the silicon nitride layer 106b is electrically affected by the potential of the floating gates FG1, FG2. That is, a fringe parasitic capacitance is generated between the floating gates FG1, FG2 and the channel in the projection 103 near the floating gates FG1, FG2. Because of such parasitic capacitance, the channel in the projection 103 is affected by the threshold voltage (Vt) modulation based on the potential of the floating gates FG1, FG2. Consequently, the parasitic capacitance causes to change the length of the channel in the projection 103 the generation of which should be controlled in accordance with the potential of the control gate CG to be supplied. Especially, in the event that the insulation layer 106 on the projection 103 is thick, the channel length in the projection 103 becomes largely affected. Moreover, the change in the channel length will affect the cell transistor 100 when the cell transistor becomes small, so it becomes a problem in reducing the size of the cell transistor 100.
The tops of the floating gates FG1, FG2 face the control gates CG in a large area. In order to discharge the electrons in the floating gates FG1, FG2 to the control gate CG effectively, the second insulation layer 105 needs to be thin. On the other hand, when the insulation layer 105 becomes thin, the coupling ratio of the floating gates FG1, FG2 (the value calculated by dividing the capacitance of the control gate CG by the capacitance of the substrate 102) increases, and the potential difference between the floating gates FG1, FG2 and the control gate CG becomes small. Thus, it is necessary to increase the voltage to be applied to the control gate CG in erasing the information. Moreover, a large coupling ratio reduces the modulation of the drain current (current window) in reading the information.
The cell transistor 100 is configured that the electrons in the floating gates FG1, FG2 is capable of being discharged through any position in the large area between the floating gates FG1, FG2 and the control gate CG. In other words, the cell transistor 100 is configured that the thickness of the second insulation layer 105 is uniform. In that case, the second insulation layer 105 is possible to contain defects, even if the second insulation layer 105 is formed by plasma oxidation (or plasma nitridation) with low possibility to generate defects. Since such defects in the second insulation layer 105 may increase the possibility to discharge the electrons, the property to accumulate electrons of the floating gates FG1, FG2 may decrease. In order to prevent this problem, it is preferable to reduce the area of the interface to discharge the electron from the floating gates FG1, FG2 to the control gate CG, and to discharge the electrons in such interface. In that case, the property or the floating gates FG1, FG2 to accumulate the electrons may be increased because of low possibility to contain defects in the second insulation layer 105.
Furthermore, the semiconductor memory has plural control gates CG (word line WL), arranged in a column direction, each of which extends in a row direction (see FIG. 1). Below the control gates CG, the projections 103 and the diffusion region (bit line BL) are alternately arranged in the row direction. In a word line formation area in which the control gate CG is formed, a pair of the floating gates FG1, FG2 is provided above the diffusion region 101 along the side of the projection 103. To manufacture such control gates CG and the floating gates FG1, FG2, a conductive material for the control gate and the floating gate needs to be electrically isolated in a separation region in the column direction. Thus, an optimum design for the separation region is required, and it is desirable to divide these conductive materials by the process to form the control gates CG and the floating gates in the column direction by self-alignment.